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C8051F380/1/2/3/4/5/6/7/C
20. Port Input/Output
Digital and analog resources are available through 40 I/O pins (C8051F380/2/4/6) or 25 I/O pins
(C8051F381/3/5/7/C). Port pins are organized as shown in Figure 20.1. Each of the Port pins can be
defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P3.7 can be assigned to one of the
internal digital resources as shown in Figure 20.3. The designer has complete control over which functions
are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is
achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always
be read in the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 20.3 and Figure 20.4). The registers XBR0, XBR1, and XBR2 defined in SFR Definition 20.1, SFR
Definition 20.2, and SFR Definition 20.3, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3,4).
XBR0, XBR1, XBR2,
PnSKIP Registers
Priority
Decoder
PnMDOUT,
PnMDIN Registers
Highest
Priority
UART0
SPI
SMBus0
2
4
2
8
P0
I/O
Cells
P0.0
P0.7
CP0
2
Outputs
CP1
Outputs
SYSCLK
PCA
T0, T1
2
6
2
Digital
Crossbar
8
8
P1
I/O
Cells
P2
I/O
Cells
P1.0
P1.7
P2.0
P2.7
Lowest
Priority
UART1
SMBus1
2
2
8
P3
I/O
Cells
P3.0
P3.7*
8
P0
P1
(P0.0-P0.7)
8
(P1.0-P1.7)
8
P2
P3
(P2.0-P2.7)
8
(P3.0-P3.7*)
*P3.1-P3.7 only available on 48-pin
packages
Figure 20.1. Port I/O Functional Block Diagram (Port 0 through Port 3)
Rev. 1.4
153
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